(1) Field of the Invention
The present invention relates to a method used to fabricate copper metal interconnect, and copper metal via structures, for semiconductor devices.
(2) Description of Prior Art
The semiconductor industry is continually attempting to increase device performance while still attempting to lower the manufacturing cost for these same semiconductor devices. The ability to create semiconductor devices with sub-micron features, or micro-miniaturization, has allowed the performance and cost objectives to be successfully addressed. For example smaller features result in decreases in performance degrading capacitances and resistances, for device regions in the semiconductor substrate. In addition the use of sub-micron features, allows smaller semiconductor chips to be realized, however still possessing device densities comparable to densities achieved with larger semiconductor chip counterparts. This allows more chips to be realized from a specific size starting substrate, thus reducing the processing cost for a specific semiconductor chip.
In addition to the performance and cost benefits attributed to micro-miniaturization, the semiconductor industry is still attempting to improve device performance by utilizing copper wiring, in place of the lower conductivity, aluminum wiring, now being used for advanced semiconductor devices. The low resistivity, about 1.7E-6 ohm-cm, of copper, would allow the use of thinner, and narrower structures, such as a dual damascene copper structure, featuring narrower via structures, and thinner overlying interconnect structures, however still providing the same desired current carrying capabilities, as thicker, and wider, aluminum interconnect and via structure counterparts. In addition, for a specific current density, copper would provide a greater degree of electromigration resistance, than aluminum based counterparts.
The use of copper interconnect structures, however, introduces several new concerns, not relevant with the aluminum based metallization. For example the thickest copper layer, used to fill a dual damascene opening, can not be realized using conventional plasma deposition procedures, and thus has to be obtained using a electro-chemical deposition, (ECD), procedure. However to effectively use the ECD procedure, an underlying copper seed layer has to be present, to initiate the deposition of the thick copper layer. The thinner copper seed layer, is obtained via plasma vapor deposition, (PVD), however this layer can present undesirable blistering, or other imperfections, as a result of an unwanted increase in deposition temperature, resulting from plasma bombardment, during the PVD procedure. The rough surface presented by the copper seed layer, is transferred to the depositing, overlying, ECD copper layer, in the form of voids. A subsequent chemical mechanical polishing, (CMP), procedure, used to define the dual damascene, copper structure, can then expose the voids in the ECD copper layer, resulting in yield or reliability failures.
This invention will provide a solution to the voids in the ECD copper layer, via a process sequence which allows a copper seed layer, with a smooth top surface topography, to be plasma deposited, and to subsequently allow the overlying ECD copper layer, to be deposited, with an absence of voids. The copper seed layer, featuring a smooth top surface topography, is obtained via a three step deposition sequence. A first step comprises deposition of a first portion of the copper seed layer, via a PVD procedure, while the second step, featuring a cool down cycle, is performed in the same, or in a different chamber, of PVD cluster tool. The third step of the sequence features the deposition of an overlying, or second portion of the copper seed layer, performed in the same chamber used for the cool down cycle, or performed in a different chamber of the cluster PVD tool. The cool down cycle, accomplished via exposing both sides of the wafer to an inert purge, does not allow the surface temperature to increase to a point, during the growth of the copper seed layer, that would result in the undesirable, rough surface topography. Prior art, such as Moran, in U.S. Pat. No. 4,657,778, describes the use of an underlying copper seed layer, prior to depositing a thick copper layer, using an ECD procedure. However that prior art does not use the three step, copper seed layer, PVD procedure, used to present a smooth top surface topography, for am overlying ECD copper layer.